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MVME2502 Installation and Use (April 2015)
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Artesyn MVME2502 Installation and Use (April 2015) User Manual Page 104
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Functional Description
MVME2502 Installation and Use (6806800R96E
)
104
4.16
Clock S
truc
ture
A total o
f three IDT c
hips, a discrete o
scillat
or and cr
ystal to suppor
t all the clock require
ments
of MVME2502.
Figure 4-3
Clock Distrib
ution Diagr
am
1
2
...
99
100
101
102
103
104
105
106
107
108
109
...
165
166
MVME2502
1
Trademarks
2
Contact Address
2
Contents
3
List of Tables
10
List of Figures
13
About this Manual
15
Abbreviations
16
Conventions
17
Summary of Changes
19
Safety Notes
21
Operation
22
Installation
22
Cabling and Connectors
23
Sicherheitshinweise
25
Kabel und Stecker
28
Batterie
28
Umweltschutz
29
Introduction
31
1.2 Standard Compliances
33
1.3 Mechanical Data
35
1.4 Ordering Information
35
1.5 Product Identification
37
Chapter 2
39
2.1 Overview
39
Shipment Inspection
40
2.3 Requirements
41
2.3.2 Power Requirements
42
2.4 Configuring the Board
43
2.5 Installing Accessories
44
2.5.2 PMC/XMC Support
46
Installation Procedure
46
HDMNTKIT2
48
MVME2502 are:
53
Chapter 3
55
3.1 Board Layout
55
3.2 Front Panel
57
3.3 LEDs
58
Table 3-1 Front Panel LEDs
59
3.3.2 On-board LEDs
60
3.4 Connectors
61
3.4.1.3 USB Connector (J5)
63
3.4.1.4 VMEBus P1 Connector
64
IRQ4 ADD 35 NC NC
65
3.4.1.5 VMEBus P2 Connector
66
3.4.2 On-board Connectors
67
3.4.2.2 PMC Connectors
68
3.4.2.3 JTAG Connector (P6)
74
3.4.2.4 COP Connector P50(15)
75
3.4.2.5 XMC Connector (XJ1)
76
3.4.2.6 XMC Connector (XJ2)
77
3.5 Switches
79
4.2 Chipset
84
4.2.3 PCI Express Interface
85
4.2.9 DMA Controller
87
4.2.14 P2020 Strapping Pins
89
4.3 System Memory
92
4.4 Timers
92
4.5 Ethernet Interfaces
93
4.6 SPI Bus Interface
94
4.6.3 Firmware Redundancy
95
4.7 Front UART Control
97
4.8 Rear UART Control
98
4.9 PMC/XMC Sites
98
4.9.1 PMC Add-on Card
99
4.9.2 XMC Add-on Card
99
4.10 SATA Interface
100
4.11 VME Support
100
4.12 USB
100
C Devices
101
4.14 Reset/Control CPLD
102
4.15 Power Management
102
Functional Description
103
4.16 Clock Structure
104
4.17 Reset Structure
105
4.18 Thermal Management
105
4.19 Real-Time Clock Battery
106
4.20 Debugging Support
106
4.20.2 JTAG Chain and Board
107
4.20.3 Custom Debugging
108
Memory Maps and Registers
111
5.3 Flash Memory Map
112
5.4 Linux Devices Memory Map
112
5.5.1 PLD Revision Register
114
5.5.2 PLD Year Register
115
5.5.3 PLD Month Register
115
5.5.4 PLD Day Register
115
5.5.5 PLD Sequence Register
116
5.5.11 PLD Boot Bank Register
121
5.5.13 PLD Test Register 1
124
5.5.14 PLD Test Register 2
125
5.5.17 EMMC Reset Register
128
5.6 External Timer Registers
130
5.6.2 Control Registers
131
Boot System
135
6.3 Boot Options
136
6.6 Updating U-Boot
143
Programming Model
145
7.3 Interrupt Controller
149
7.4 I2C Bus Device Addressing
150
7.5 Ethernet PHY Address
150
7.6.1 MRAM
151
7.6.2 Real Time Clock
151
7.6.3 Quad UART
151
7.6.4 LBC Timing Parameters
152
7.7 Clock Distribution
153
7.7.1 System Clock
154
7.7.2 Real Time Clock Input
155
Replacing the Battery
157
Related Documentation
161
B.2 Manufacturers’ Documents
162
B.3 Related Specifications
162
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