Artesyn MVME6100 Single Board Computer Installation and Us User Manual Page 69
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Functional Description
MVME6100 Single Board Computer Installation and Use (6806800D58H)
69
PCI bus 0 is connected to the Tsi148 device and PMCspan bridge. PCI bus 0 is configured for 133
MHz PCI-X mode.
The MV64360 PCI interfaces are fully PCI rev. 2.2 and PCI-X rev 1.0 compliant and support both
address and data parity checking. The MV64360 contains all of the required PCI configuration
registers. All internal registers, including the PCI configuration registers, are accessible from
the CPU bus or the PCI buses.
4.6.5 Gigabit Ethernet MACs
The MVME6100 supports two 10/100/1000Mb/s full duplex Ethernet ports connected to the
front panel via the MV64360 system controller. Ethernet access is provided by front panel RJ-
45 connectors with integrated magnetics and LEDs. Port 1 is a dedicated Gigabit Ethernet port
while a configuration header is provided for port 2 front or rear P2 access Refer to Front/Rear
Ethernet and Transition Module Options Header (J30) for more information.
Each Ethernet interface is assigned an Ethernet Station Address. The address is unique for each
device. The Ethernet Station Addresses are displayed on labels attached to the PMC front-panel
keep-out area.
The MV64360 is not integrated with a PHY for the Ethernet interfaces. External PHY is the
Broadcom BCM5461S 10/100/1000BaseT Gigabit transceiver with SERDES interface. Refer to
Appendix C, Related Documentation for more information.
4.6.6 SRAM
The MV64360 integrates 2Mb of general-purpose SRAM. It is accessible from the CPU or any of
the other interfaces. It can be used as fast CPU access memory (6 cycles latency) and for off
loading DRAM traffic. A typical usage of the SRAM can be a descriptor RAM for the Gigabit
Ethernet ports.
4.6.7 General-Purpose Timers/Counters
There are four 32-bit wide timers/counters on the MV64360. Each timer/counter can be
selected to operate as a timer or as a counter. The timing reference is based on the MV64360
Tclk input, which is set at 133 MHz. Each timer/counter is capable of generating an interrupt.
Refer to the MV64360 Data Sheet, listed in Appendix C, Related Documentation, for additional
information and programming details.
- Installation and Use 1
- Trademarks 2
- Contact Address 2
- Contents 3
- List of Tables 7
- List of Figures 10
- About this Manual 11
- Abbreviations 12
- Conventions 14
- Summary of Changes 15
- Chapter 1 17
- 1.1 Overview 17
- 1.2 Description 17
- 1.3 Declaration of Conformity 19
- 1.4 Getting Started 20
- 1.5 Configuring the Hardware 21
- Figure 1-2 Component Layout 23
- J30 Options 27
- 1.6 Installing the Blade 30
- 1.7 Connecting to Peripherals 30
- Startup and Operation 33
- MOTLoad Firmware 35
- 3.3.2 Tests 36
- 3.3.3 Command List 37
- MOTLoad Firmware 38
- 3.4.1 Command Line Rules 44
- 3.4.2 Command Line Help 44
- 3.5 Firmware Settings 45
- 3.5.3 Displaying VME Settings 49
- 3.5.4 Editing VME Settings 50
- 3.5.5 Deleting VME Settings 51
- 3.6 Remote Start 52
- 3.10 Boot Images 56
- 3.10.2 Image Flags 57
- 3.10.3 User Images 58
- 3.11 Startup Sequence 61
- Functional Description 63
- 4.3 Block Diagram 65
- 4.4 Processor 65
- 4.5 L3 Cache 66
- 4.6 System Controller 66
- 4.6.1 CPU Bus Interface 67
- 4.6.4 PCI/PCI-X Interfaces 68
- 4.6.5 Gigabit Ethernet MACs 69
- 4.6.6 SRAM 69
- 4.6.12 Interrupt Controller 71
- 4.7 VMEbus Interface 72
- 4.8 PMCspan Interface 72
- 4.9 Flash Memory 72
- 4.10 System Memory 73
- 4.12 PCI Mezzanine Card Slots 73
- 4.14 IDSEL Routing 75
- 4.15 Reset Control Logic 75
- 4.16 Debug Support 75
- 5.2.4 COM1 Connector (J19) 92
- 5.2.5 VMEbus P1 Connector 93
- 5.3 Headers 100
- 5.3.1 SCON Header (J7) 101
- 5.3.4 COM2 Header (J29) 102
- Pin Assignments 103
- Specifications 105
- Thermal Validation 107
- B.3.1 Preparation 111
- Related Documentation 115
- C.3 Related Specifications 117
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