Artesyn ATCA-9305 User's Manual (May 2014) User Manual download pdf (Page 82)

Cavium Processor Complex

ATCA-9305 User’s Manual (10009109-07)

3.5.2 RLDRAM

Each CN5860 supports 256 MB Common I/O (CIO) RLDRAM operating up to 400 MHz

(depends on the processor speed). The Micron RLDRAM II is organized as 32Mx18x8 internal

banks. The DDR I/O interface transfers two data words per clock cycle. Output data is

referenced to the free-running output data clock. Read and write accesses to the RLDRAM are

burst-oriented. RLDRAM is accessed by using Cavium-specific instructions which operate on

MIPS Coprocessor 2. SCP variants of the ATCA-9305 do not support RLDRAM.

3.5.3 I

C EEPROM

Each Cavium processor complex has one user EEPROM device for parameter storage located on

the I

C bus, address 0xA8. The I

C bus for each processor is completely independent from the

other CN5860 processor and MPC8548 processor I

C buses. The Atmel two-wire serial

EEPROM on each CN5860 processor I

C interface consists of the Serial Clock (SCL) input and

the Serial Data (SDA) bidirectional lines.

3.5.4 Flash, 512 KB x 8

The 512 KB of 32-pin PLCC socketed flash starts at physical address1D46,0000

and is used

for Engineering code. The StrataFlash features high-performance fast asynchronous access

times, low power, and flexible security options.

3.5.5 Flash, 4 MB x 16

The 4 MB soldered NOR flash starts at physical address 1D05,0000

. The 32-Mbit device

provides CN5860 code storage and non-volatile memory.

Table 3-7 Cavium NVRAM Memory Map

Address Offset (hex) Description Window Size (bytes)

0x1E00-0x1FFF Monitor parameters 256

0x0000-0x1D36 User defined 79F

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 269 270

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Artesyn ATCA-9305 User's Manual (May 2014) User Manual Page 82