Artesyn ATCA-9305 User's Manual (May 2014) User Manual Page 106
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Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07)
106
5.1.1 Product ID
This read-only register identifies the board as ATCA-9305, and is used for PLD coding.
0x58 LFTR1 Low Frequency Timer 1 118
0x5C LFTR2 Low Frequency Timer 2 118
0x60 RGSR RTM GPIO State 119
0x64 RGCR RTM GPIO Control 119
0x68 RTMCR RTM Control 120
0x70 CMUL1 Cavium 1 C_MUL Clock Divisor Control 121
0x74 CMUL2 Cavium 2 C_MUL Clock Divisor Control 121
0x78 JTAG Altera JTAG Chain Software Control 122
0x80 CGCR Cavium GPIO Control 123
0x84 CGDO Cavium GPIO Data Out 123
0x88 CGDI Cavium GPIO Data In 124
0x8C IGCR IPMP/IPMC GPIO Control 125
0xD0 LPC1 Low Pin Count (LPC) Bus Control 125
0xD4 LPCD LPC Data 126
0xD8 SIRQI1 Serial IRQ Interrupt 1 [15:8] 126
0xDC SIRQI2 Serial IRQ Interrupt 2 [7:0] 127
Table 5-1 PLD Register Summary (continued)
Address Offset
(hex) Mnemonic Register Name See Page
Scratch 1 (0x40) is a read/write register for storage only.
Table 5-2 Product ID (0x00)
Bits Function Description
7 CAVF1 Cavium Frequency 1
6 CAVF0 Cavium Frequency 0
- ATCA-9305 1
- Trademarks 2
- Contact Address 2
- EMC Compliance 3
- GR-1089-CORE STANDARD 4
- Contents 10
- List of Tables 15
- List of Figures 19
- Safety Notes 21
- Installation 22
- Operation 23
- Hot Swap 23
- RJ-45 Connectors 24
- Replacement/Expansion 24
- Environment 24
- Sicherheitshinweise 25
- Board Installation 26
- RJ-45 Stecker 28
- Austausch/Erweiterung 29
- Umweltschutz 29
- About this Manual 31
- Conventions 34
- Summary of Changes 36
- Overview 37
- 1.2 Functional Overview 40
- 1.3 Additional Information 41
- 1.3.2 RoHS Compliance 42
- Chapter 2 47
- 2.1 Electrostatic Discharge 47
- 2.2 ATCA-9305 Circuit Board 48
- ATCA-9035 49
- StrataFlash 54
- COMPONENT MAP 55
- SCALE 1/1 55
- TOP VIEW 57
- CR56 CR57 58
- BOTTOM VIEW 59
- SW 4700SW 4700 59
- 2.2.1 Connectors 60
- 2.2.2 Configuration Header 61
- 2.3 ATCA-9305 Setup 62
- 2.3.3 Hot Swap 66
- 2.4 Troubleshooting 67
- 2.4.2 Product Repair 68
- Cavium Processor Complex 69
- 3.1.1 Cavium Memory Map 70
- 3.2.1 CN5860 Boot Over PCI 72
- 3.2.2 Cavium Reset 73
- 3.3 Cavium Ethernet 75
- 3.4 Cavium Monitor 76
- 3.4.2 Power-up/Reset Sequence 77
- 3.5 Memory 81
- 3.5.2 RLDRAM 82
- C EEPROM 82
- 3.5.4 Flash, 512 KB x 8 82
- 3.5.5 Flash, 4 MB x 16 82
- 3.6 StratixGX Interconnect 83
- 3.6.1.2 Address Registers 85
- 3.6.1.3 Control Register 86
- 3.6.1.4 Version Register 87
- 3.6.1.5 Scratch Register 87
- 3.7 Headers and Connectors 89
- 3.7.2 Console Serial Ports 90
- 4.1.1 MPC8548 Memory Map 93
- 4.1.2 Chip Selects 97
- 4.2 Memory 99
- Management Complex 100
- 4.2.2.2 4M 100
- 4.2.2.3 1 GB(optional) 100
- 4.2.2.4 64 MB 100
- C INTERFACE 101
- 4.5.2 Serial Debug Port 104
- Management Processor CPLD 105
- 5.1.1 Product ID 106
- 5.1.2 Hardware Version 107
- 5.1.3 PLD Version 108
- 5.1.4 PLL Reset Configuration 108
- 5.1.6 Jumper Settings 109
- 5.1.7 LED 110
- 5.1.8 Reset Event 111
- 5.1.9 Reset Command 1 112
- 5.1.10 Reset Command 2 112
- 5.1.11 Reset Command 3 113
- 5.1.12 Reset Command 4 114
- 5.1.13 Reset Command 5 114
- 5.1.17 Miscellaneous Control 117
- 5.1.19 RTM GPIO State 119
- 5.1.20 RTM GPIO Control 119
- 5.1.21 RTM Status 120
- 5.1.24 JTAG 122
- 5.1.25 Cavium GPIO Control 123
- 5.1.26 Cavium GPIO Data Out 123
- 5.1.27 Cavium GPIO Data In 124
- 5.1.28 IPMP/IPMC GPIO Control 125
- 5.1.29 LPC Bus Control 125
- 5.1.30 LPC Data 126
- 5.1.31 Serial IRQ Interrupt 1 126
- 5.1.32 Serial IRQ Interrupt 2 127
- Ethernet Interface 129
- 6.2.1 Ethernet Transceivers 132
- 6.2.2 Ethernet Switch Ports 132
- 6.2.3 VLAN Setup 133
- System Management 137
- 7.3 IPMI Messaging 139
- 7.3.1 IPMI Completion Codes 140
- 7.4 IPMB Protocol 142
- 7.5 SIPL Protocol 143
- [B8 00 01 0A 40 00 12] 144
- 7.6 Message Bridging 145
- 7.7 Standard Commands 147
- 7.8 OEM Boot Options 150
- 7.9.1 Watchdog Timer Actions 152
- 7.10 FRU LEDs 159
- 7.11 Vendor Commands 167
- 7.11.1 Get Status 168
- 7.11.4 Get Debug Level 174
- 7.11.5 Set Debug Level 175
- 7.11.6 Get Hardware Address 176
- 7.11.7 Set Hardware Address 176
- 7.11.8 Get Handle Switch 177
- 7.11.9 Set Handle Switch 177
- 7.11.14 Reset IPMC 180
- 7.11.15 Hang IPMC 181
- 7.11.16 Bused Resource 182
- 7.11.17 Bused Resource Status 183
- 7.11.18 Graceful Reset 185
- 7.16 MESSAGE LISTENERS 198
- 7.20 FRU Inventory 207
- 7.21 E-Keying 208
- 7.22 HPM.1 Firmware Upgrade 210
- 7.23 IPMC Headers 211
- Back Panel Connectors 213
- 8.3 Zone 2 215
- 8.4 Zone 3 216
- Management Processor Monitor 219
- 9.3 Basic Operation 222
- 9.3.1 Power-up/Reset Sequence 223
- 9.3.2 POST Diagnostic Results 224
- 9.3.3 Monitor SDRAM Usage 225
- 9.5 Monitor Command Reference 228
- 9.6 Boot Commands 229
- 9.6.4 bootp 230
- 9.6.5 bootv 230
- 9.6.6 bootvx 231
- 9.6.7 dhcp 231
- 9.6.8 rarpboot 232
- 9.7 File Load Commands 233
- 9.8 Memory Commands 234
- 9.8.1 cmp 235
- 9.8.2 cp 235
- 9.8.3 find 235
- 9.8.4 md 236
- 9.8.5 mm 237
- 9.8.6 nm 238
- 9.8.7 mw 238
- 9.9 Flash Commands 239
- 9.9.3 flinfo 240
- 9.9.4 protect 240
- 9.10 EEPROM/I 241
- C Commands 241
- 9.10.3 iloop 242
- 9.10.4 imd 242
- 9.10.5 imm 242
- 9.10.6 imw 242
- 9.11 IPMC Commands 243
- 9.11.2 bparams_get 244
- 9.11.3 bparams_set 244
- 9.11.4 fru 245
- 9.11.5 fruinit 246
- 9.11.6 fruled 246
- 9.11.7 ipmchpmfw 247
- 9.11.8 sensor 247
- 9.12.1 printenv 248
- 9.12.2 saveenv 248
- 9.12.3 setenv 248
- 9.13 Test Commands 249
- 9.14 Other Commands 250
- 9.14.4 coninfo 251
- 9.14.5 crc32 251
- 9.14.6 date 251
- 9.14.7 echo 251
- 9.14.8 enumpci 252
- 9.14.9 go 252
- 9.14.10 help 252
- 9.14.11 iminfo 252
- 9.14.12 isdram 253
- 9.14.13 loop 253
- 9.14.14 memmap 253
- 9.14.15 moninit 253
- 9.14.16 pci 254
- 9.14.17 phy 255
- 9.14.18 ping 255
- 9.14.19 reset 255
- 9.14.20 run 256
- 9.14.21 script 256
- 9.14.22 showmac 257
- 9.14.23 showpci 257
- 9.14.24 sleep 257
- 9.14.25 switch_reg 257
- 9.14.26 version 258
- 9.14.27 vlan 258
- 9.16 Troubleshooting 263
- 9.17 Download Formats 263
- 9.17.1 Binary 264
- 9.17.2 Motorola S-Record 264
- Related Documentation 265
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